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features monolithic cmos a/d converters microprocessor compatible parallel and serial output inherent track/hold input true 12, 14 and 16-bit precision conversion times: cs5016 16.25 m s cs5014 14.25 m s cs5012a 7.20 m s self calibration maintains accuracy over time and temperature low power dissipation: 150 mw low distortion general description the cs5012a/14/16 are 12, 14 and 16-bit monolithic analog to digital converters with conversion times of 7.2 m s, 14.25 m s and 16.25 m s. unique self-calibration cir- cuitry insures excellent linearity and differential non- linearity, with no missing codes. offset and full scale errors are kept within 1/2 lsb (cs5012a/14) and 1 lsb (cs5016), eliminating the need for calibration. unipolar and bipolar input ranges are digitally select- able. the pin compatible cs5012a/14/16 consist of a dac, conversion and calibration microcontroller, oscillator, comparator, microprocessor compatible 3-state i/o, and calibration circuitry. the input track-and-hold, in- herent to the devices sampling architecture, acquires the input signal after each conversion using a fast slewing on-chip buffer amplifier. this allows throughput rates up to 100 khz (cs5012a), 56 khz (cs5014) and 50 khz (cs5016). an evaluation board (cdb5012/14/16) is available which allows fast evaluation of adc performance. ordering information: pages 2-45, 2-46, & 2-47 mar 95 ds14f6 2-7 crystal semiconductor corporation p.o. box 17847, austin, tx 78760 (512) 445 7222 fax: (512) 445 7581 16, 14 & 12-bit, self-calibrating a/d converters semiconductor corporation cs5016 cs5014 cs5012a d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 (msb) d4 (lsb) cs5012a 6 7 8 9 12 13 14 15 16 17 18 19 d2 (lsb) cs5014 d0 (lsb) cs5016 d1 sclk eot eoc sdata 2 3 4 5 37 38 39 40 d3 clkin clock generator 20 intrlv 34 rst 32 21 a0 23 rd 22 hold 1 bw 33 24 cal 35 cs bp/up refbuf agnd 29 vref 28 ain 26 27 charge redistribution dac comparator va+ va- vd+ vd- dgnd tst 25 30 11 36 10 31 + - + - + - + - control calibration memory microcontroller status register copyright ? crystal semiconductor corporation 1995 (all rights reserved)
cs5012a cs5012a analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 2.5v to 4.5v; f clk = 6.4 mhz for -7, 4 mhz for -12; analog source impedance = 200 w ) cs5012a-k cs5012a-b cs5012-t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c accuracy linearity error (note 1) drift (note 2) 1/4 1/8 1/2 1/4 1/8 1/2 1/4 1/8 1/2 lsb 12 d lsb 12 differential linearity (note 1) drift (note 2) 1/4 1/32 1/2 1/4 1/32 1/2 1/4 1/32 1/2 lsb 12 d lsb 12 full scale error (note 1) drift (note 2) 1/4 1/16 1/2 1/4 1/16 1/2 1/4 1/8 1/2 lsb 12 d lsb 12 unipolar offset (note 1) drift (note 2) 1/4 1/16 1/2 1/4 1/16 1/2 1/4 1/16 1/2 lsb 12 d lsb 12 bipolar offset (note 1) drift (note 2) 1/4 1/16 1/2 1/4 1/16 1/2 1/4 1/16 1/2 lsb 12 d lsb 12 bipolar negative full-scale error(note 1) drift (note 2) 1/4 1/16 1/2 1/4 1/16 1/2 1/4 1/16 1/2 lsb 12 d lsb 12 total unadjusted error (note 1) drift (note 2) 1/4 1/4 1/4 1/4 1/4 1/4 lsb 12 d lsb 12 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise full scale, 1 khz input full scale, 12 khz input 84 84 92 88 84 84 92 88 84 84 92 88 db db total harmonic distortion 0.008 0.008 0.008 % signal-to-noise ratio (note 1) 1 khz, 0 db input 1 khz, -60 db input 72 73 13 72 73 13 72 73 13 db db noise (note 3) unipolar mode bipolar mode 45 90 45 90 45 90 m v rms m v rms notes: 1. applies after calibration at any temperature within the specified temperature range. 2. total drift over specified temperature range since calibration at power-up at 25 c 3. wideband noise aliased into the baseband. referred to the input. * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subject to change without notice. 2-8 ds14f6
cs5012a analog characteristics (continued) cs5012a-k cs5012a-b cs5012-t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c analog input aperture time 25 25 25 ns aperture jitter 100 100 100 ps input capacitance (note 4) unipolar mode cs5012 cs5012a bipolar mode cs5012 cs5012a 275 103 165 72 375 137 220 96 275 103 165 72 375 137 220 96 275 103 165 72 375 137 220 96 pf pf pf pf conversion & throughput conversion time -7 (notes 5 and 6) -12 7.2 12.25 7.2 12.25 12.25 m s m s acquisition time -7 (note 6) -12 2.5 3.0 2.8 3.75 2.5 3.0 2.8 3.75 3.0 3.75 m s m s throughput -7 (note 6) -12 100 62.5 100 62.5 62.5 khz khz power supplies dc power supply currents (note 7) i a + i a - (cs5012) i d + (cs5012a) i d + i d - 12 -12 3 6 -3 19 -19 6 7.5 -6 12 -12 3 6 -3 19 -19 6 7.5 -6 12 -12 3 -3 19 -19 6 -6 ma ma ma ma ma power dissipation (note 7) 150 250 150 250 150 250 mw power supply rejection (note 8) positive supplies negative supplies 84 84 84 84 84 84 db db notes: 4. applies only in track mode. when converting or calibrating, input capacitance will not exceed 15 pf. 5. measured from falling transition on hold to falling transition on eoc. 6. conversion, acquisition, and throughput times depend on clkin, sampling, and calibration conditions. the numbers shown assume sampling and conversion is synchronized with the cs5012a/14/16 s conversion clock, interleave calibrate is disabled, and operation is from the full-rated, external clock. refer to the section conversion time/throughput for a detailed discussion of conversion timing. 7. all outputs unloaded. all inputs cmos levels. 8. with 300 mv p-p, 1 khz ripple applied to each analog supply separately in bipolar mode. rejection improves by 6 db in the unipolar mode to 90 db. figure 13 shows a plot of typical power supply rejection versus frequency. cs5012a ds14f6 2-9
cs5014 analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 4.5v; clkin = 4 mhz for -14, 2 mhz for -28; analog source impedance = 200 w ) cs5014-k cs5014-b cs5014-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c accuracy linearity error k, b, t (note 1) s drift (note 2) 1/4 1/8 1/2 1/4 1/8 1/2 1/4 1/2 1/8 1/2 1.5 lsb 14 lsb 14 d lsb 14 differential linearity (note 1) drift (note 2) 1/4 1/32 1/2 1/4 1/32 1/2 1/4 1/32 1/2 lsb 14 d lsb 14 full scale error (note 1) drift (note 2) 1/2 1/4 1 1/2 1/4 1 1/2 1/2 1 lsb 14 d lsb 14 unipolar offset k, b, t (note 1) s drift (note 2) 1/4 1/4 3/4 1/4 1/4 3/4 1/4 1/2 3/4 1 lsb 14 lsb 14 d lsb 14 bipolar offset k, b, t (note 1) s drift (note 2) 1/4 1/4 3/4 1/4 1/2 3/4 1/4 1/2 3/4 1 lsb 14 lsb 14 d lsb 14 bipolar negative full-scale error(note 1) k, b, t s drift (note 2) 1/2 1/4 1 1/2 1/4 1 1/2 1/2 1 1.5 lsb 14 lsb 14 d lsb 14 total unadjusted error (note 1) drift (note 2) 1 1/2 1 1 1 1 lsb 14 d lsb 14 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise full scale, 1 khz input k, b, t s full scale, 12 khz input k, b, t s 94 84 98 87 94 84 98 87 94 85 84 80 98 87 db db db db total harmonic distortion 0.003 0.003 0.003 % signal-to-noise ratio (notes 1 and 9) 1 khz, 0 db input k, b, t s 1 khz, -60 db input 82 84 23 82 84 23 82 80 84 23 db db db noise (note 3) unipolar mode bipolar mode 45 90 45 90 45 90 m v rms m v rms notes: 9. a detailed plot of s/(n+d) vs. input amplitude appears in figure 26 for the cs5014 and figure 28 for the cs5016. * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subject to change without notice. cs5014 2-10 ds14f6
cs5014 cs5014 analog characteristics (continued) cs5014-k cs5014-b cs5014-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c analog input aperture time 25 25 25 ns aperture jitter 100 100 100 ps input capacitance (note 4) unipolar mode bipolar mode 275 165 375 220 275 165 375 220 275 165 375 220 pf pf conversion & throughput conversion time -14 (notes 5 and 6) -28 14.25 28.5 14.25 28.5 14.25 28.5 m s m s acquisition time -14 (note 6) -28 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 m s m s throughput -14 (note 6) -28 55.6 27.7 55.6 27.7 55.6 27.7 khz khz power supplies dc power supply currents (note 7) i a + i a - i d + i d - 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 ma ma ma ma power dissipation (note 7) 120 250 120 250 120 250 mw power supply rejection (note 8) positive supplies negative supplies 84 84 84 84 84 84 db db ds14f6 2-11
cs5016 cs5016 analog characteristics (t a = t min to t max ; va+, vd+ = 5v; va-, vd- = -5v; vref = 4.5v; clkin = 4 mhz for -16, 2 mhz for -32; analog source impedance = 200 w ; synchronous sampling.) cs5016-j, k cs5016-a, b cs5016-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c accuracy linearity error j, a, s (note 1) k, b, t drift (note 2) 0.002 0.001 1/4 0.003 0.0015 0.002 0.001 1/4 0.003 0.0015 0.002 0.001 1/4 0.0076 0.0015 %fs %fs d lsb 16 differential linearity (note 10) 16 16 16 bits full scale error j, a, s (note 1) k, b, t drift (note 2) 2 2 1 3 3 2 2 1 3 3 2 2 2 4 3 lsb 16 lsb 16 d lsb 16 unipolar offset j, a, s (note 1) k, b, t drift (note 2) 1 1 1 2 3/2 1 1 1 3 3 1 1 2 4 3 lsb 16 lsb 16 d lsb 16 bipolar offset j, a, s (note 1) k, b, t drift (note 2) 1 1 1 2 3/2 1 1 2 2 2 1 1 2 4 2 lsb 16 lsb 16 d lsb 16 bipolar negative full-scale error(note 1) j, a, s k, b, t drift (note 2) 2 2 1 3 3 2 2 2 3 3 2 2 2 5 3 lsb 16 lsb 16 d lsb 16 dynamic performance (bipolar mode) peak harmonic or (note 1) spurious noise full scale, 1 khz input j, a, s k, b, t full scale, 12 khz input j, a, s k, b, t 96 100 85 85 100 104 88 91 96 100 85 85 100 104 88 91 92 100 82 85 100 104 88 91 db db db db total harmonic distortion j, a, s full scale, 1 khz input k, b, t 0.002 0.001 0.002 0.001 0.002 0.001 % % signal-to-noise ratio (notes 1 and 9) 1 khz, 0 db input j, a, s k, b, t 1 khz, -60 db input j, a, s k, b, t 87 90 90 92 30 32 87 90 90 92 30 32 84 90 90 92 30 32 db db db db noise (note 3) unipolar mode bipolar mode 35 70 35 70 35 70 m v rms m v rms notes: 10. minimum resolution for which no missing codes is guaranteed * refer to parameter definitions (immediately following the pin descriptions at the end of this data sheet). specifications are subject to change without notice. 2-12 ds14f6
cs5016 cs5016 analog characteristics (continued) cs5016-j, k cs5016-a, b cs5016-s, t parameter* min typ max min typ max min typ max units specified temperature range 0 to +70 -40 to +85 -55 to +125 c analog input aperture time 25 25 25 ns aperture jitter 100 100 100 ps input capacitance (note 4) unipolar mode bipolar mode 275 165 375 220 275 165 375 220 275 165 375 220 pf pf conversion & throughput conversion time -16 (notes 5 and 6) -32 16.25 32.5 16.25 32.5 16.25 32.5 m s m s acquisition time -16 (note 6) -32 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 3.0 4.5 3.75 5.25 m s m s throughput -16 (note 6) -32 50 26.5 50 26.5 50 26.5 khz khz power supplies dc power supply currents (note 7) i a + i a - i d + i d - 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 9 -9 3 -3 19 -19 6 -6 ma ma ma ma power dissipation (note 7) 120 250 120 250 120 250 mw power supply rejection (note 8) positive supplies negative supplies 84 84 84 84 84 84 db db ds14f6 2-13
switching characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%; inputs: logic 0 = 0v, logic 1 = vd+; c l = 50 pf, bw = vd+) parameter symbol min typ max units cs5012a clkin frequency: internally generated: externally supplied: -7 -12 f clk 1.75 100 khz 100 khz - - - - 6.4 4.0 mhz mhz mhz cs5014/5016 clkin frequency: internally generated: -14, -16 -28, -32 externally supplied: -14, -16 -28, -32 f clk 1.75 1 100 khz 100 khz - - - - - - 4 2 mhz mhz mhz mhz clkin duty cycle 40 - 60 % rise times: any digital input any digital output t rise - - - 20 1.0 - m s ns fall times: any digital input any digital output t fall - - - 20 1.0 - m s ns hold pulse width t hpw 1/f clk +50 - t c ns conversion time: cs5012a cs5014 cs5016 t c 49/f clk +50 57/f clk 65/f clk - - - 53/f clk +235 61/f clk +235 69/f clk +235 ns ns ns data delay time t dd - 40 100 ns eoc pulse width (note 11) t epw 4/f clk -20 - - ns set up times: cal, intrlv to cs low a0 to cs and rd low t cs t as 20 20 10 10 - - ns ns hold times: cs or rd high to a0 invalid cs high to cal, intrlv invalid t ah t ch 50 50 30 30 - - ns ns access times: cs low to data valid a, b, j, k s, t rd low to data valid a, b, j, k s, t t ca t ra - - - - 90 115 90 90 120 150 120 150 ns ns ns ns output float delay: k, b cs or rd high to output hi-z t t fd - - 90 90 110 140 ns ns serial clock pulse width low pulse width high t pwl t pwh - - 2/f clk 2/f clk - - ns ns set up times: sdata to sclk rising t ss 2/f clk -50 2/f clk -ns hold times: sclk rising to sdata t sh 2/f clk -100 2/f clk -ns notes: 11. eoc remains low 4 clkin cycles if cs and rd are held low. otherwise, it returns high within 4 clkin cycles from the start of a data read operation or a conversion cycle. cs5012a, cs5014, cs5016 2-14 ds14f6
90% 10% t fall rise t 90% 10% hi-z hi-z ch t t cs t ah t fd t as t ra t ca hold eoc output data t hpw t c last conversion data valid t dd new data valid t epw d0-d15 a0 cs rd cal, intrlv sdata t ss t sh sclk t pwl t pwh rise and fall times conversion timing serial output timing read and calibration control timing cs5012a, cs5014, cs5016 ds14f6 2-15
cs5012a, cs5014, cs5016 digital characteristics (t a = t min to t max ; va+, vd+ = 5v 10%; va-, vd- = -5v 10%) parameter symbol min typ max units high-level input voltage v ih 2.0 - - v low-level input voltage v il --0.8v high-level output voltage (note 12) v oh (vd+) - 1.0v - - v low-level output voltage i out = 1.6ma v ol --0.4v input leakage current i in --10 m a 3-state leakage current i oz -- 10 m a digital output pin capacitance c out -9-pf notes: 12. i out = -100 m a. this specification guarantees ttl compatibility (v oh = 2.4v @ i out = -40 m a). recommended operating conditions (agnd, dgnd = 0v, see note 13) parameter symbol min typ max units dc power supplies: positive digital negative digital positive analog negative analog vd+ vd- va+ va- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 va+ -5.5 5.5 -5.5 v v v v analog reference voltage vref 2.5 4.5 (va+) - 0.5 v analog input voltage: (note 14) unipolar bipolar v ain v ain agnd -vref - - vref vref v v notes: 13. all voltages with respect to ground. 14. the cs5012a/14/16 can accept input voltages up to the analog supplies (va+ and va-). it will output all 1s for inputs above vref and all 0s for inputs below agnd in unipolar mode and -vref in bipolar mode. absolute maximum ratings (agnd, dgnd = 0v, all voltages with repect to ground.) warning: operation at or beyond these limits may reult in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min max units dc power supplies: positive digital (note 15) negative digital positive analog negative analog vd+ vd- va+ va- -0.3 0.3 -0.3 0.3 6.0 -6.0 6.0 -6.0 v v v v input current, any pin except supplies (note 16) i in - 10 ma analog input voltage (ain and vref pins) v ina (va-) - 0.3 (va+) + 0.3 v digital input voltage v ind -0.3 (va+) + 0.3 v ambient operating temperature t a -55 125 c storage temperature t stg -65 150 c notes: 15. in addition, vd+ should not be greater than (va+) + 0.3v. 16. transient currents of up to 100 ma will not cause scr latch-up. 2-16 ds14f6
theory of operation the cs5012a/14/16 family utilize a successive approximation conversion technique. the analog input is successively compared to the output of a d/a converter controlled by the conversion algo- rithm. successive approximation begins by comparing the analog input to the dac output which is set to half-scale (msb on, all other bits off). if the input is found to be below half-scale, the msb is reset to zero and the input is com- pared to one-quarter scale (next msb on, all others off). if the input were above half-scale, the msb would remain high and the next compari- son would be at three-quarters of full scale. this procedure continues until all bits have been exer- cised. a unique charge redistribution architecture is used to implement the successive approximation algorithm. instead of the traditional resistor net- work, the dac is an array of binary-weighted capacitors. all capacitors in the array share a common node at the comparators input. their other terminals are capable of being connected to ain, agnd, or vref (figure 1). when the de- vice is not calibrating or converting, all capacitors are tied to ain forming c tot . switch s1 is closed and the charge on the array, q in , tracks the input signal v in (figure 2a). when the conversion command is issued, switch s1 opens as shown in figure 2b. this traps charge q in on the comparator side of the capaci- tor array and creates a floating node at the comparators input. the conversion algorithm op- erates on this fixed charge, and the signal at the analog input pin is ignored. in effect, the entire dac capacitor array serves as analog memory ain vref agnd cc/2 c/4 c/8 msb lsb bit 11 bit 10 bit 9 bit 8 bit 0 dummy c/x s1 bit 13 bit 15 bit 12 bit 14 bit 11 bit 13 bit 10 bit 12 cs5012a: cs5014: cs5016: c/x x = 2048 x = 8192 x = 32768 cs5012a cs5014 cs5016 c = c + c/2 + c/4 + ... + c/x tot figure 1. charge redistribution dac (1-d) c tot in q + - v fn to mcu s1 c tot d . vref agnd d for vref v in =0v fn v = figure 2b. convert mode in q c tot s1 v in ain + - to mcu = v in c tot in -q figure 2a. tracking mode cs5012a, cs5014, cs5016 ds14f6 2-17
during conversion much like a hold capacitor in a sample/hold amplifier. the conversion consists of manipulating the free plates of the capacitor array to vref and agnd to form a capacitive divider. since the charge at the floating node remains fixed, the voltage at that point depends on the proportion of capaci- tance tied to vref versus agnd. the successive-approximation algorithm is used to find the proportion of capacitance, termed d in figure 2b, which when connected to the refer- ence will drive the voltage at the floating node (v fn ) to zero. that binary fraction of capacitance represents the converters digital output. this charge redistribution architecture easily sup- ports bipolar input ranges. if half the capacitor array (the msb capacitor) is tied to vref rather than ain in the track mode, the input range is doubled and is offset half-scale. the magnitude of the reference voltage thus defines both positive and negative full-scale (-vref to +vref), and the digital code is an offset binary representation of the input. calibration the ability of the cs5012a/14/16 to convert ac- curately clearly depends on the accuracy of their comparator and dac. the cs5012a/14/16 util- ize an "auto-zeroing" scheme to null errors introduced by the comparator. all offsets are stored on the capacitor array while in the track mode and are effectively subtracted from the in- put signal when a conversion is initiated. auto-zeroing enhances power supply rejection at frequencies well below the conversion rate. to achieve complete accuracy from the dac, the cs5012a/14/16 use a novel self-calibration scheme. each bit capacitor, shown in figure 1, actually consists of several capacitors which can be manipulated to adjust the overall bit weight. an on-chip microcontroller adjusts the subarrays to precisely ratio the bits. each bit is adjusted to just balance the sum of all less significant bits plus one dummy lsb (for example, 16c = 8c + 4c + 2c + c + c). calibration resolution for the array is a small fraction of an lsb resulting in nearly ideal differential and integral linearity. digital circuit connections the cs5012a/14/16 can be applied in a wide va- riety of master clock, sampling, and calibration conditions which directly affect the devices con- version time and throughput. the devices also feature on-chip 3-state output buffers and a com- plete interface for connecting to 8-bit and 16-bit digital systems. output data is also available in serial format. master clock the cs5012a/14/16 operate from a master clock (clkin) which can be externally supplied or in- ternally generated. the internal oscillator is activated by externally tying the clkin input low. alternatively, the cs5012a/14/16 can be synchronized to the external system by driving the clkin pin with a ttl or cmos clock sig- nal. clkin master clock (optional) hold eot cs5012a/14/16 figure 3b. synchronous sampling clkin master clock (optional) hold sampling clock cs5012a/14/16 figure 3a. asynchronous sampling cs5012a, cs5014, cs5016 2-18 ds14f6
all calibration, conversion, and throughput times directly scale to clkin frequency. thus, throughput can be precisely controlled and/or maximized using an external clkin signal. in contrast, the cs5012a/14/16s internal oscillator will vary from unit-to-unit and over temperature. the cs5012a/14/16 can typically convert with clkin as low as 10 khz at room temperature. initiating conversions a falling transition on the hold pin places the input in the hold mode and initiates a conversion cycle. upon completion of the conversion cycle, the cs5012a/14/16 automatically return to the track mode. in contrast to systems with separate track-and-holds and a/d converters, a sampling clock can simply be connected to the hold in- put (figure 3a). the duty cycle of this clock is not critical. it need only remain low at least one clkin cycle plus 50 ns, but no longer than the minimum conversion time or an additional con- version cycle will be initiated with inadequate time for acquisition. microprocessor-controlled operation sampling and conversion can be placed under microprocessor control (figure 4) by simply gat- ing the devices decoded address with the write strobe for the hold input. thus, a write cycle to the cs5012a/14/16s base address will initiate a conversion. however, the write cycle must be to the odd address (a0 high) to avoid initiating a software controlled reset (see reset below). the calibration control inputs, cal, and intrlv are inputs to a set of transparent latches. these signals are internally latched by cs return- ing high. they must be in the appropriate state whenever the chip is selected during a read or write cycle. address lines a1 and a2 are shown connected to cal and intrlv in figure 4 plac- ing calibration under microprocessor control as well. thus, any read or write cycle to the cs5012a/14/16s base address will initiate or ter- minate calibration. alternatively, a0, intrlv, and cal may be connected to the microproces- sor data bus. conversion time/throughput upon completing a conversion cycle and return- ing to the track mode, the cs5012a/14/16 require time to acquire the analog input signal before another conversion can be initiated. the acquisition time is specified as six clkin cycles plus 2.25 m s (1.32 m s for the cs5012a -7 version only). this adds to the conversion time to define the converters maximum throughput. the con- version time of the cs5012a/14/16, in turn, depends on the sampling, calibration, and clkin conditions. hold cs5012a/14/16 addr dec a3 an address bus wr rd cs rd intrlv a2 a1 cal a0 a0 addr valid figure 4b. conversions under microprocessor control cs5012a/14/16 cs addr dec a3 an address bus rd rd conclk hold intrlv cal a0 a2 a1 a0 addr valid figure 4a. conversions asynchronous to clkin cs5012a, cs5014, cs5016 ds14f6 2-19
asynchronous sampling the cs5012a/14/16 internally operate from a clock which is delayed and divided down from clkin (f clk /4). if sampling is not synchronized to this internal clock, the conversion cycle may not begin until up to four clock cycles after hold goes low even though the charge is trapped immediately. in this asynchronous mode (figure 3a), the four clock cycles add to the mini- mum 49, 57 and 65 clock cycles (for the cs5012a/14/16 respectively) to define the maxi- mum conversion time (see figure 5a and table 1). synchronous sampling to achieve maximum throughput, sampling can be synchronized with the internal conversion clock by connecting the end-of-track ( eot) out- put to hold (figure 3b). the eot output falls 15 clkin cycles after eoc indicating the ana- log input has been acquired to the cs5012a/14/16s specified accuracy. the eot output is synchronized to the internal conversion clock, so the four clock cycle synchronization un- certainty is removed yielding throughput at [1/64]f clk for the cs5012a, [1/72]f clk for cs5014 and [1/80]f clk for cs5016 where f clk is the clkin frequency (see figure 5b and ta- ble 1). * conversion (49 + n cycles) 1 / throughput (64 + n cycles) output eot output eoc input hold acquisition (15 cycles) * dashed line: cs & rd = 0 cs5012a n = 0 solid line: see figure 9 cs5014 n = 8 cs5016 n = 16 figure 5b. synchronous (loopback mode) conversion synchronization uncertainty (4 cycles) input output output acquisition hold eoc eot 1 / throughput figure 5a. asynchronous sampling (external clock) throughput time conversion time sampling mode synchronous (loopback) asynchronous min 64 t clk n/a n/a max 64 t clk 59 1.32 m s t clk + 59 2.25 m s t clk + max + 235 ns 53 t clk 49 t clk + 235 ns 53 t clk min 49 t clk 49 t clk 49 t clk -7 -12,-24 cs5012a cs5014 57 t clk 57 t clk + 235 ns 61 t clk 57 t clk 72 t clk n/a 72 t clk 67 2.25 m s t clk + synchronous (loopback) asynchronous 65 t clk 65 t clk + 235 ns 69 t clk 65 t clk 80 t clk n/a 80 t clk 75 2.25 m s t clk + synchronous (loopback) asynchronous cs5016 table 1. conversion and throughput times (t clk = master clock period) cs5012a, cs5014, cs5016 2-20 ds14f6
also, the cs5012a/14/16s internal rc oscillator exhibits jitter (typically 0.05% of its period), which is high compared to crystal oscillators. if the cs5012a/14/16 is configured for synchro- nous sampling while operating from its internal oscillator, this jitter will directly affect sampling purity. the user can obtain best sampling purity while synchronously sampling by using an exter- nal crystal-based clock. reset upon power up, the cs5012a/14/16 must be re- set to guarantee a consistent starting condition and initially calibrate the devices. due to the cs5012a/14/16s low power dissipation and low temperature drift, no warm-up time is required before reset to accommodate any self-heating ef- fects. however, the voltage reference input should have stabilized to within 5%, 1% or 0.25% of its final value, for the cs5012a/14/16 respectively, before rst falls to guarantee an ac- curate calibration. later, the cs5012a/14/16 may be reset at any time to initiate a single full cali- bration. reset overrides all other functions. if reset, the cs5012a/14/16 will clear and initiate a new calibration cycle mid-conversion or mid-cali- bration. resets can be initiated in hardware or software. the simplest method of resetting the cs5012a/14/16 involves strobing the rst pin high for at least 100 ns. when rst is brought high all internal logic clears. when it returns low, a full calibration begins which takes 58,280 clkin cycles for the cs5012a (approximately 9.1 ms with a 6.4 mhz clock) and 1,441,020 clkin cycles for the cs5016, cs5014 and cs5012 (approximately 360 ms with a 4 mhz clkin). a simple power-on reset circuit can be built using a resistor and capacitor, and a schmitt-trigger inverter to prevent oscillation (see figure 6). the cs5012a/14/16 can also be reset in software when under microprocessor control. the cs5012a/14/16 will reset whenever cs, a0, and hold are taken low simultaneously. see the microprocessor interface section (below) to eliminate the possibility of inadvertent software reset. the eoc output remains high throughout the calibration operation and will fall upon its completion. it can thus be used to generate an interrupt indicating the cs5012a/14/16 is ready for operation. while calibrating, the hold input is ignored until eoc falls. after eoc falls, six clkin cycles plus 2.25 m s (1.32 m s for the cs5012a -7 version only) must be allowed for signal acquisition before hold is activated. un- der microprocessor-independent operation ( cs, rd low; a0 high) the cs5014s and cs5016s eoc output will not fall at the completion of the calibration cycle, but eot will fall 15 clkin cycles later. initiating calibration all modes of calibration can be controlled in hardware or software. accuracy can thereby be insured at any time or temperature throughout op- erating life. after initial calibration at power-up, the cs5012a/14/16s charge-redistribution design yields better temperature drift and more graceful aging than resistor-based technologies, so calibra- tion is normally only required once, after power-up. the first mode of calibration, reset, results in a single full calibration cycle. the second type of calibration, "burst" cal, allows control of partial calibration cycles. due to an unforeseen con- didtion inside the part, asynchronous termination of calibration may result in a sub-optimal result. burst cal should not be used. c r +5v rst cs5012a/14/16 figure 6. power-on reset circuit cs5012a, cs5014, cs5016 ds14f6 2-21
the reset calibration always works perfectly, and should be used instead of burst mode. the cs5012s and cs5012a/14/16s very low drift over temperature means that, under most circum- stances, calibration will only need to be performed at power-up, using reset. the cs5012a/14/16 feature a background cali- bration mode called "interleave." interleave appends a single calibration experiment to each conversion cycle and thus requires no dead time for calibration. the cs5012a/14/16 gathers data between conversions and will adjust its transfer function once it completes the entire sequence of experiments (one calibration cycle per 2,014 con- versions in the cs5012a and one calibration per 72,051 conversions in the cs5012, cs5014 and cs5016). initiated by bringing both the intrlv input and cs low (or hard-wiring intrlv low), interleave extends the cs5012a/14/16s effective conversion time by 20 clkin cycles. other than reduced throughput, interleave is totally transpar- ent to the user. interleave calibration should not be used intermittently. the fact that the cs5012a/14/16 offer several calibration modes is not to imply that the devices need to be recalibrated often. the devices are very stable in the presence of large temperature changes. tests have indicated that after using a single reset calibration at 25 c most devices ex- hibit very little change in offset or gain when exposed to temperatures from -55 to +125 c. the data indicated 30 ppm as the typical worst case total change in offset or gain over this tem- perature range. differential linearity remained virtually unchanged. system error sources outside of the a/d converter, whether due to changes in temperature or to long-term aging, will generally dominate total system error. microprocessor interface the cs5012a/14/16 feature an intelligent micro- processor interface which offers detailed status information and allows software control of the self-calibration functions. output data is available in either 8-bit or 16-bit formats for easy interfac- ing to industry-standard microprocessors. strobing both cs and rd low enables the cs5012a/14/16s 3-state output buffers with either output data or status information depending on the status of a0. an address bit can be con- nected to a0 as shown in figure 4b thereby memory mapping the status register and output data. conversion status can be polled in software by reading the status register ( cs and rd strobed low with a0 low), and masking status bits s0-s5 and s7 (by logically anding the status word with 01000000) to determine the value of s6. similarly, the software routine can determine calibration status using other status bits (see ta- ble 2). care must be taken not to read the status register (a0 low) while hold is low, or a soft- ware reset will result (see reset above). alternatively, the end-of-convert ( eoc) output can be used to generate an interrupt or drive a dma controller to dump the output directly into memory after each conversion. the eoc pin falls as each conversion cycle is completed and data is valid at the output. it returns high within four clkin cycles of the first subsequent data read operation or after the start of a new conversion cycle. cs5012a, cs5014, cs5016 2-22 ds14f6
to interface with a 16-bit data bus, the bw input to the cs5012a/14/16 should be held high and all data bits (12, 14 and 16 for the cs5012a, cs5014 and cs5016 respectively) read in paral- lel on pins d4-d15 (cs5012a), d2-d15 (cs5014), or d0-d15 (cs5016). with an 8-bit bus, the converters result must be read in two portions. in this instance, bw should be held low and the 8 msbs obtained on the first read cycle following a conversion. the second read cycle will yield the remaining lsbs (4, 6 or 8 for the cs5012a/14/16 respectively) with 4, 2 or 0 trail- ing zeros. both bytes appear on pins d0-d7. the upper/lower bytes of the same data will continue to toggle on subsequent reads until the next con- version finishes. status bit s2 indicates which byte will appear on the next data read operation. the cs5012a/14/16 internally buffer their output data, so data can be read while the devices are tracking or converting the next sample. therefore, retrieving the converters digital output requires no reduction in adc throughput. enabling the 3- state outputs while the cs5012a/14/16 is converting will not introduce conversion errors. connecting cmos logic to the digital outputs is recommended. suitable logic families include 4000b, 74hc, 74ac, 74act, and 74hct. pin status bit status definition d0 s0 end of conversion falls upon completion of a conversion, and returns high on the first subsequent read. d1 s1 reserved reserved for factory use. d2 s2 low byte/ high byte when data is to be read in an 8-bit format (bw=0), indicates which byte will appear at the output next. d3 s3 end of track when low, indicates the input has been acquired to the devices specified accuracy. d4 s4 reserved reserved for factory use. d5 s5 tracking high when the device is tracking the input. d6 s6 converting high when the device is converting the held input. d7 s7 calibrating high when the device is calibrating. table 2. status pin definitions d7 d0 d5 d3 d2 d1 d6 d4 d12 d11 d10 d9 d8 d15 d14 d13 xxx xx x x x s7 s6 s5 s4 s3 s2 s1 s0 8- or 16-bit data bus data (a0=1) status (a0=0) "x" denotes high impedance output xxx xx x xx 8-bit bus (bw=0) 16-bit bus (bw=1) b5 b4 b11 b10 b7 b6 b8 b9 cs5012a cs5014 cs5016 b13 b11 b9 b7 b6 b12 b10 b8 b5 b4 b11 b10 b7 b6 b8 b9 b15 b13 b11 b9 b8 b14 b12 b10 b3 b2 b1 b0 0 0 00 b5 b4 b3 b2 0 0 b1 b0 b7 b6 b5 b4 b1 b0 b3 b2 b3 b2 b1 b0 0 0 00 xxx xx x xx b7 b6 b13 b12 b9 b8 b10 b11 b5 b4 b3 b2 0 0 b1 b0 xxx xx x xx b9 b8 b15 b14 b11 b10 b12 b13 b7 b6 b5 b4 b1 b0 b3 b2 cs5016 cs5014 cs5012a figure 7. cs5012a/14/16 data format cs5012a, cs5014, cs5016 ds14f6 2-23
microprocessor independent operation the cs5012a/14/16 can be operated in a stand- alone mode independent of intelligent control. in this mode, cs and rd are hard-wired low. this permanently enables the 3-state output buffers and allows transparent latch inputs (cal and intrlv) to be active. a free-running condition is established when bw is tied high, cal is tied low, and hold is continually strobed low or tied to eot. the cs5012a/14/16s eoc output can be used to externally latch the output data if de- sired. with cs and rd hard-wired low, eoc will strobe low for four clkin cycles after each con- version. data will be unstable up to 100 ns after eoc falls, so it should be latched on the rising edge of eoc. serial output all successive-approximation a/d converters de- rive their digital output serially starting with the msb. the cs5012a/14/16 present each bit to the sdata pin four clkin cycles after it is derived and can be latched using the serial clock output, sclk. just subsequent to each bit decision sclk will fall and return high once the bit infor- mation on sdata has stabilized. thus, the rising edge of the sclk output should be used to clock the data from the cs5012a/14/16 (see figure 9). analog circuit connections most popular successive-approximation a/d con- verters generate dynamic loads at their analog connections. the cs5012a/14/16 internally buff- er all analog inputs (ain, vref, and agnd) to ease the demands placed on external circuitry. however, accurate system operation still requires careful attention to details at the design stage re- garding source impedances as well as grounding and decoupling schemes. reference considerations an application note titled " voltage references for the cs501x series of a/d converters " is avail- able for the cs5012a/14/16. in addition to working through a reference circuit design exam- ple, it offers several built-and-tested reference circuits. during conversion, each capacitor of the cali- brated capacitor array is switched between vref and agnd in a manner determined by the suc- cessive-approximation algorithm. the charging and discharging of the array results in a current load at the reference. the cs5012a/14/16 in- clude an internal buffer amplifier to minimize the external reference circuits drive requirement and preserve the references integrity. whenever the array is switched during conversion, the buffer is used to pre-charge the array thereby providing the bulk of the necessary charge. the appropriate array capacitors are then switched to the unbuf- fered vref pin to avoid any errors due to offsets and/or noise in the buffer. the external reference circuitry need only pro- vide the residual charge required to fully charge the array after pre-charging from the buffer. this creates an ac current load as the cs5012a/14/16 sequence through conversions. the reference cir- cuitry must have a low enough output impedance to drive the requisite current without changing its output voltage significantly. as the analog input signal varies, the switching sequence of the inter- nal capacitor array changes. the current load on the external reference circuitry thus varies in re- sponse with the analog input. therefore, the external reference must not exhibit significant bw cal rst reset a0 cs hold +5v sampling clock rd d4 d15 data out 12-bit eoc latching output intrlv cs5012a cs5014 cs5016 figure 8. microprocessor-independent connections cs5012a, cs5014, cs5016 2-24 ds14f6
peaking in its output impedance characteristic at signal frequencies or their harmonics. a large capacitor connected between vref and agnd can provide sufficiently low output im- pedance at the high end of the frequency spectrum, while almost all precision references exhibit extremely low output impedance at dc. the magnitude of the current load on the external reference circuitry will scale to the clkin fre- quency. at full speed, the reference must supply a maximum load current of 10 m a peak-to-peak (1 m a typical). for the cs5012a an output im- pedance of 15 w will therefore yield a maximum error of 150 mv. with a 2.5v reference and lsb size of 600 mv, this would insure better than 1/4 lsb accuracy. a 1 m f capacitor exhibits an im- pedance of less than 15 w at frequencies greater than 10 khz. similarly, for the cs5014 with a 4.5v reference (275 m v/lsb), better than 1/4 lsb accuracy can be insured with an output impedance of 4 w or less (maximum error of 40 m v). a 2.2 m f capacitor exhibits an imped- ance of less than 4 w at frequencies greater than 5khz. for the cs5016 with a 4.5v reference (69 m v/lsb), better than 1/4 lsb accuracy can be insured with an output impedance of less than 2 w (maximum error of 20 m v). a 20 m f capaci- tor exhibits an impedance of less than 2 w at frequencies greater than 16 khz. a high-quality tantalum capacitor in parallel with a smaller ce- ramic capacitor is recommended. clkin eoc status eot hold sclk sdata t d t d determined lsb fine charge determined msb determined msb - 1 determined msb - 2 coarse charge lsb+1 lsb msb msb - 1 lsb+2 246 8 10 12 64 62 60 80/0 76 78 74 72 70 68 66 cs5016: 246 8 10 12 56 54 72/0 68 70 66 64 62 60 58 52 cs5014: 246 8 10 12 48 46 44 64/0 60 62 58 56 54 52 50 cs5012a: figure 9. serial output timing notes: 1. synchronous (loopback) mode is illustrated. after eoc falls the converter goes into coarse charge mode for 6 clkin cycles, then to fine charge mode for 9 cycles, then eot falls. in loopback mode, eot trips hold which captures the analog sample. conversion begins on the next rising edge of clkin. if operated asynchro- nously, eot will remain low until after hold is taken low. when hold occurs the analog sample is captured immediately, but conversion may not begin until four clkin cycles later. eot will return high when conversion begins. 2. timing delay t d (relative to clkin) can vary between 135 ns to 235 ns over the military temperature range and over 10% supply variation 3. eoc returns high in 4 clkin cycles if a0 = 1 and cs = rd = 0 (microprocessor independent mode); within 4 clkin cycles after a data read (microprocessor mode); or 4 clkin cycles after hold = 0 is recognized on a rising edge of clkin/4. cs5012a, cs5014, cs5016 ds14f6 2-25
peaking in the references output impedance can occur because of capacitive loading at its output. any peaking that might occur can be reduced by placing a small resistor in series with the capaci- tors (figure 10). the equation in figure 10 can be used to help calculate the optimum value of r for a particular reference. the term "f peak " is the frequency of the peak in the output impedance of the reference before the resistor is added. the cs5012a/14/16 can operate with a wide range of reference voltages, but signal-to-noise performance is maximized by using as wide a signal range as possible. the recommended refer- ence voltage is between 2.5 and 4.5 v for the cs5012a and 4.5 v for the cs5014/16. the cs5012a/14/16 can actually accept reference voltages up to the positive analog supply. how- ever, the buffers offset may increase as the reference voltage approaches va+ thereby in- creasing external drive requirements at vref. a 4.5v reference is the maximum reference voltage recommended. this allows 0.5v headroom for the internal reference buffer. also, the buffer en- lists the aid of an external 0.1 m f ceramic capacitor which must be tied between its output, refbuf, and the negative analog supply, va-. for more information on references, consult the applica- tion note: voltage references for the cs501x se- ries of a/d converters. for an example of using the cs5012a/14/16 with a 5 volt reference, see the application note: a collection of application hints for the cs501x series of a/d converters. analog input connection the analog input terminal functions similarly to the vref input after each conversion when switching into the track mode. during the first six clkin cycles in the track mode, the buffered version of the analog input is used for pre-charg- ing the capacitor array. an additional period is required for fine-charging directly from ain to vref refbuf va- 0.1 m f -5v r 29 28 30 ref v c1 1.0 m f 0.01 m f c2 +v ee cs5012a cs5014 cs5016 1 r= 2 p (c 1 + c 2 ) f peak figure 10. reference connections internal charge error (lsb's) fine-charge pre-charge acquisition time (us) 0.5 1.0 1.5 2.0 2.5 (delay from eoc) +12.5 0 -12.5 -25.0 +50 0 -50 -100 +200 0 -200 -400 cs5012a cs5014 cs5016 figure 11. internal acquisition time cs5012a, cs5014, cs5016 2-26 ds14f6
obtain the specified accuracy. figure 11 illustrates this operation. during pre-charge the charge on the capacitor array first settles to the buffered ver- sion of the analog input. this voltage is offset from the actual input voltage. during fine-charge, the charge then settles to the accurate unbuffered version. the acquisition time of the cs5012a/14/16 de- pends on the clkin frequency. this is due to a fixed pre-charge period. for instance, operating the cs5012a -12, cs5014 -14 or cs5016 -16 version with an external 4 mhz clkin results in a 3.75 m s acquisition time: 1.5 m s for pre-charging (6 clock cycles) and 2.25 m s for fine-charging. fine-charge settling is specified as a maximum of 2.25 m s for an analog source impedance of less than 200 w . (for the cs5012a -7 version it is specified as 1.32 m s.) in addition, the comparator requires a source impedance of less than 400 w around 2 mhz for stability, which is met by prac- tically all bipolar op amps. large dc source impedances can be accommodated by adding ca- pacitance from ain to ground (typically 200 pf) to decrease source impedance at high frequencies. however, high dc source resistances will increase the inputs rc time constant and extend the nec- essary acquisition time. for more information on input applications, consult the application note: input buffer amplifiers for the cs501x family of a/d converters . during the first six clock cycles following a con- version (pre-charge) in unipolar mode, the cs5012a is capable of slewing at 20v/ m s and the cs5014/16 can slew at 5v/ m s. in bipolar mode, only half the capacitor array is connected to the analog input so the cs5012a can slew at 40v/ m s, and the cs5014/16 can slew at 10v/ m s. after the first six clkin cycles, the cs5012a will slew at 1.25v/ m s in unipolar mode and 3.0v/ m s in bipolar mode, and the cs5014/16 will slew at 0.25v/ m s in unipolar mode and 0.5v/ m s in bipolar mode. acquisition of fast slewing signals (step func- tions) can be hastened if the step occurs during or immediately following the conversion cycle. for instance, channel selection in multiplexed appli- cations should occur while the cs5012a/14/16 is converting (see figure 12). multiplexer settling is thereby removed from the overall throughput equation, and the cs5012a/14/16 can convert at full speed. convert channel n+1 convert channel n address n address n + 1 address n + 2 address n + 3 eoc output hold input mux address mux settling to channel n + 2 analog input mux settling to channel n + 1 cs5012a/14/16 cs5012a/14/16 cs5012a/14/16 figure 12. pipelined mux input channels cs5012a, cs5014, cs5016 ds14f6 2-27
analog input range/coding format the reference voltage directly defines the input voltage range in both the unipolar and bipolar configurations. in the unipolar configuration (bp/ up low), the first code transition occurs 0.5 lsb above agnd, and the final code transi- tion occurs 1.5 lsbs below vref. coding is in straight binary format. in the bipolar configura- tion (bp/ up high), the first code transition occurs 0.5 lsb above -vref and the last transition oc- curs 1.5 lsbs below +vref. coding is in an offset-binary format. positive full scale gives a digital output of all ones, and negative full scale gives a digital output of all zeros. the bp/ up mode pin may be switched after cali- bration without having to recalibrate the converter. however, the bp/ up mode should be changed during the previous conversion cycle, that is, between hold falling and eoc falling. if bp/ up is changed at any other time, one dummy conversion cycle must be allowed for proper acquisition of the input. grounding and power supply decoupling the cs5012a/14/16 use the analog ground con- nection, agnd, only as a reference voltage. no dc power currents flow through the agnd con- nection, and it is completely independent of dgnd. however, any noise riding on the agnd input relative to the systems analog ground will induce conversion errors. therefore, both the ana- log input and reference voltage should be referred to the agnd pin, which should be used as the entire systems analog ground reference point. the digital and analog supplies to the cs5012a/14/16 are pinned out separately to minimize coupling between the analog and digital sections of the chip. all four supplies should be decoupled to their respective grounds using 0.1 m f ceramic capacitors. if significant low-fre- quency noise is present on the supplies, 1 m f tantalum capacitors are recommended in parallel with the 0.1 m f capacitors. the positive digital power supply of the cs5012a/14/16 must never exceed the positive analog supply by more than a diode drop or the device could experience permanent damage. if the two supplies are derived from separate sources, care must be taken that the analog sup- ply comes up first at power-up. the system connection diagram in figure 36 shows a decou- pling scheme which allows the cs5012a/14/16 to be powered from a single set of 5v rails. as with any high-precision a/d converter, the cs5012a/14/16 require careful attention to grounding and layout arrangements. however, no unique layout issues must be addressed to prop- erly apply the device. the cdb5012/14/16 evaluation board is available for the cs5012a/14/16, which avoids the need to de- sign, build, and debug a high-precision pc board to initially characterize the part. the board comes with a socketed cs5012a/14/16, and can be quickly reconfigured to simulate any combination of sampling, calibration, clkin, and analog in- put range conditions. cs5012a, cs5014, cs5016 2-28 ds14f6
power supply rejection the cs5012a/14/16s power supply rejection performance is enhanced by the on-chip self-cali- bration and an "auto-zero" process. drifts in power supply voltages at frequencies less than the calibration rate have negligible effect on the cs5012a/14/16s accuracy. this is because the cs5012a/14/16 adjust their offset to within a small fraction of an lsb during calibration. above the calibration frequency the excellent power supply rejection of the internal amplifiers is augmented by an auto-zero process. any offsets are stored on the capacitor array and are effectively subtracted once conversion is initiated. figure 13 shows power supply rejection of the cs5012a/14/16 in the bipolar mode with the analog input grounded and a 300 mvp-p ripple applied to each supply. power supply rejection improves by 6 db in the unipolar mode. the plot in figure 13 shows worst-case rejection for all combinations of conversion rates and input conditions in the bipolar mode. cs5012a/14/16 performance differential nonlinearity one source of nonlinearity in a/d converters is bit weight errors. these errors arise from the de- viation of bits from their ideal binary-weighted ratios, and lead to nonideal widths for each code. if dnl errors are large, and code widths shrink to zero, it is possible for one or more codes to be entirely missing. the cs5012a/14/16 calibrate all bits in the capacitor array to a small fraction of an lsb resulting in nearly ideal dnl. histo- gram plots of typical dnl of the cs5012a/14/16 can be seen in figures 14, 16, 17. figure 15 il- lustrates the dnl of the cs5012 for comparison with the cs5012a (figure 14). a histogram test is a statistical method of deriv- ing an a/d converters differential nonlinearity. a ramp is input to the a/d and a large number of samples are taken to insure a high confidence level in the tests result. the number of occur- rences for each code is monitored and stored. a perfect a/d converter would have all codes of equal size and therefore equal numbers of occur- rences. in the histogram test a code with the average number of occurrences will be consid- ered ideal (dnl = 0). a code with more or less occurrences than average will appear as a dnl of greater or less than zero lsb. a missing code has zero occurrences, and will appear as a dnl of -1 lsb. integral nonlinearity integral nonlinearity (inl; also termed relative accuracy or just nonlinearity) is defined as the deviation of the transfer function from an ideal straight line. bows in the transfer curve generate harmonic distortion. the worst-case condition of bit-weight errors (dnl) has traditionally also de- fined the point of maximum inl. bit-weight errors have a drastic effect on a con- verters ac performance. they can be analyzed as step functions superimposed on the input signal. power supply ripple frequency 1 khz 10 khz 100 khz 1 mhz power supply rejection (db) 90 80 70 60 50 40 30 20 figure 13. power supply rejection cs5012a, cs5014, cs5016 ds14f6 2-29
0 4,095 codes 2,048 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 14. cs5012a differential nonlinearity plot 0 4,095 codes 2,048 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 15. cs5012 differential nonlinearity plot 0 16,383 codes 8,192 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 16. cs5014 differential nonlinearity plot 0 65,535 codes 32,768 dnl (lsb) +1 0 -1 +1/2 -1/2 figure 17. cs5016 differential nonlinearity plot cs5012a, cs5014, cs5016 2-30 ds14f6
since bits (and their errors) switch in and out throughout the transfer curve, their effect is sig- nal dependent. that is, harmonic and intermodulation distortion, as well as noise, can vary with different input conditions. designing a system around characterization data is risky since transfer curves can differ drastically unit-to-unit and lot-to-lot. the cs5012a/14/16 achieves repeatable signal- to-noise and harmonic distortion performance using an on-chip self-calibration scheme. the cs5012a calibrates its bit weight errors to a small fraction of an lsb at 12-bits yielding peak distortion below the noise floor (see figure 19). the cs5014 calibrates its bit weights to within 1/16 lsb at 14-bits ( 0.0004% fs) yielding peak distortion as low as -105 db (see fig- ure 22). the cs5016 calibrates its bit weights to within 1/4 lsb at 16-bits ( 0.0004% fs) yield- ing peak distortion as low as -105 db (see figure 24). unlike traditional adcs, the linear- ity of the cs5012a/14/16 are not limited by bit-weight errors; their performance is therefore extremely repeatable and independent of input signal conditions. quantization noise the error due to quantization of the analog input ultimately dictates the accuracy of any a/d con- verter. the continuous analog input must be represented by one of a finite number of digital codes, so the best accuracy to which an analog input can be known from its digital code is 1/2 lsb. under circumstances commonly en- countered in signal processing applications, this quantization error can be treated as a random variable. the magnitude of the error is limited to 1/2 lsb, but any value within this range has equal probability of occurrence. such a prob- ability distribution leads to an error "signal" with an rms value of 1 lsb/ ? 12. using an rms signal value of fs/ ? 8 (amplitude = fs/2), this relates to ideal 12, 14 and 16-bit signal-to-noise ratios of 74, 86 and 98 db respectively. equally important is the spectral content of this error signal. it can be shown to be approximately white, with its energy spread uniformly over the band from dc to one-half the sampling rate. ad- vantage of this characteristic can be made by judicious use of filtering. if the signal is ban- dlimited, much of the quantization error can be filtered out, and improved system performance can be attained. fft tests and windowing in the factory, the cs5012a/14/16 are tested us- ing fast fourier transform (fft) techniques to analyze the converters dynamic performance. a pure sinewave is applied to the cs5012a/14/16, and a "time record" of 1024 samples is captured and processed. the fft algorithm analyzes the spectral content of the digital waveform and dis- tributes its energy among 512 "frequency bins." assuming an ideal sinewave, distribution of en- ergy in bins outside of the fundamental and dc can only be due to quantization effects and errors in the cs5012a/14/16. if sampling is not synchronized to the input sine- wave, it is highly unlikely that the time record will contain an integer number of periods of the input signal. however, the fft assumes that the signal is periodic, and will calculate the spectrum of a signal that appears to have large discontinui- ties, thereby yielding a severely distorted spectrum. to avoid this problem, the time record is multiplied by a window function prior to per- forming the fft. the window function smoothly forces the endpoints of the time record to zero, thereby removing the discontinuities. the effect of the window in the frequency-domain is to con- volute the spectrum of the window with that of the actual input. figure 18 shows an fft computed from an ideal 12-bit sinewave. the quality of the window used for harmonic analysis is typically judged by its highest side-lobe level. the blackman-harris window used for testing the cs5014 and cs5016 has a maximum side-lobe level of -92 db. fig- cs5012a, cs5014, cs5016 ds14f6 2-31
ures 21 and 23 show fft plots computed from an ideal 14 and 16-bit sinewave multiplied by a blackman-harris window. artifacts of window- ing are discarded from the signal-to-noise calculation using the assumption that quantization noise is white. all fft plots in this data sheet were derived by averaging the fft results from ten 1024 point time records. this filters the spec- tral variability that can arise from capturing finite time records without disturbing the total energy outside the fundamental. all harmonics which ex- ist above the noise floor and the -92 db side-lobes from the blackman-harris window are therefore clearly visible in the plots. for more in- formation on ffts and windowing refer to: f.j. harris, "on the use of windows for harmonic dc 50.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 sampling rate: 100khz full scale: 9vp-p s/n+d: 72.9db input frequency (khz) 12.0 signal amplitude relative to full scale (db) figure 20. fft plot of cs5012a with 12 khz full-scale input dc -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 input frequency signal amplitude relative to full scale (db) s/n+d: 73.9 db f /2 s figure 18. plot of ideal 12-bit adc dc 50.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 0.0 input frequency (khz) 1.0 signal amplitude relative to full scale (db) sampling rate: 100khz full scale: 9vp-p s/n+d: 73.6db figure 19. plot of cs5012a with 1 khz full scale input signal amplitude relative to full scale dc 0db -20db -40db -60db -80db -100db -120db 28 khz 1 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 85.3 db input frequency figure 22. cs5014 fft plot with 1 khz full scale input signal amplitude relative to full scale dc input frequency s/(n+d): 86.1 db 0db -20db -40db -60db -80db -100db -120db f /2 s figure 21. plot of ideal 14-bit adc cs5012a, cs5014, cs5016 2-32 ds14f6
analysis with the discrete fourier transform", proc. ieee, vol. 66, no. 1, jan 1978, pp.51-83. this is available on request from crystal semi- conductor. figures 19, 22, and 24 show the performance of the cs5012a/14/16 with 1khz full scale inputs. figure 20 shows cs5012a performance with 12khz full scale inputs. notice that the perform- ance cs5012a/14/16 closely approaches that of the corresponding ideal adc. cs5012a high frequency performance the cs5012a performs very well over a wide range of input frequencies as shown in figure 25. the figure depicts the cs5012a-kp7 tested un- der four different conditions. the conditions include tests with the voltage reference set at 4.5 and at 2.5 volts with input signals at 0.5 db down from full scale and 6.0 db down from full scale. the sample rate is at 100 khz for all cases. the plots indicate that the part performs very well even with input frequencies above the nyquist rate. best performance at the higher frequencies is achieved with a 2.5 volt reference. 0 20 40 60 80 100 120 140 160 180 200 55 60 65 70 75 signal to noise + distortion input frequency (khz) /2 f s f s cs5012a-kp7 f s =100 khz 2 1 3 4 4.5 2.5 4.5 2.5 fs-0.5db fs-0.5db fs-6.0db fs-6.0db 1. 2. 3. 4. vref signal (db) figure 25. cs5012a high frequency input performance signal amplitude relative to full scale dc input frequency s/(n+d): 97.5 db 0db -20db -40db -60db -80db -100db -120db f /2 s figure 23. plot of ideal 16-bit adc signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 92.4 db 1 khz figure 24. cs5016 fft plot with 1 khz full scale input cs5012a, cs5014, cs5016 ds14f6 2-33
signal to noise + distortion vs signal level as illustrated in figures 26 - 29, the cs5014/16s on-chip self-calibration provides very accurate bit weights which yield no degradation in quantiza- tion noise with low-level input signals. in fact, quantization noise remains below the noise floor in the cs5016, which dictates the converters sig- nal-to-noise performance. cs5016 noise considerations all analog circuitry in the cs5016 is wideband in order to achieve fast conversions and high throughput. wideband noise in the cs5016 inte- grates to 35 m v rms in unipolar mode (70 m v rms in bipolar mode). this is approximately 1/2 lsb rms with a 4.5v reference in both modes. figure 30 shows a histogram plot of output code occur- rences obtained from 5000 samples taken from a cs5016 in the bipolar mode. hexadecimal code 80cd was arbitrarily selected and the analog in- put was set close to code center. with a noiseless converter, code 80cd would always appear. the histogram plot of the cs5016 has a "bell" shape with all codes other than 80cd due to internal noise. in a sampled data system all information about the analog input applied to the sample/hold appears in the baseband from dc to one-half the sampling rate. this includes high-frequency components which alias into the baseband. low-pass (anti-alias) filters analog input amplitude -100 db -80 db -60 db -40 db -20 db 0 db 100 db 80 db 60 db 40 db 20 db 0 db s(n+d) 1 khz 12 khz 24 khz input frequencies figure 26. cs5014 s/(n+d) vs. input amplitude (9vp-p full-scale input) analog input amplitude -100 db -80 db -60 db -40 db -20 db 0 db 100 db 80 db 60 db 40 db 20 db 0 db s(n+d) 1 khz 12 khz 24 khz input frequency figure 28. cs5016 s/(n+d) vs. input amplitude (9vp-p full-scale input) signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz 1 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 24.1 db figure 27. cs5014 fft plot with 1 khz -60 db input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 9.6 db 1 khz figure 29. cs5016 fft plot with 1 khz -80 db input cs5012a, cs5014, cs5016 2-34 ds14f6
are therefore used to remove frequency compo- nents in the input signal which are above one-half the sample rate. however, all wideband noise in- troduced by the cs5016 still aliases into the baseband. this "white" noise is evenly spread from dc to one-half the sampling rate and inte- grates to 35 m v rms in unipolar mode. noise can be reduced by sampling at higher than the desired word rate and averaging multiple samples for each word. oversampling spreads the cs5016s noise over a wider band (for lower noise density), and averaging applies a low-pass response which filters noise above the desired signal bandwidth. in general, the cs5016s noise performance can be maximized in any application by always sampling at the maximum specified rate of 50 khz (for lowest noise density) and digitally filtering to the desired signal bandwidth. cs5014 and cs5016 sampling distortion the ultimate limitation on the cs5014/16s linearity (and distortion) arises from nonideal sampling of the analog input voltage. the cali- brated capacitor array used during conversions is also used to track and hold the analog input sig- nal. the conversion is not performed on the analog input voltage per se, but is actually per- formed on the charge trapped on the capacitor ar- ray at the moment the hold command is given. the charge on the array is ideally related to the analog input voltage by q in = -v in x c tot as shown in figure 2. any deviation from this ideal relationship will result in conversion errors even if the conversion process proceeds flawlessly. at dc, the dac capacitor arrays voltage coeffi- cient dictates the converters linearity. this variation in capacitance with respect to applied signal voltage yields a nonlinear relationship be- tween charge q in and the analog input voltage v in and places a bow or wave in the transfer function. this is the dominant source of distor- tion at low input frequencies (figures 22 and 24). the ideal relationship between q in and v in can also be distorted at high signal frequencies due to nonlinearities in the internal mos switches. dy- namic signals cause ac current to flow through the switches connecting the capacitor array to the analog input pin in the track mode. nonlinear on- resistance in the switches causes a nonlinear voltage drop. this effect worsens with increased signal frequency as shown in figures 26 and 28 since the magnitude of the steady state current in- creases. first noticeable at 1 khz, this distortion assumes a linear relationship with input fre- quency. with signals 20 db or more below full-scale, it no longer dominates the converters overall s/(n+d) performance (figures 31-34). this distortion is strictly an ac sampling phe- nomenon. if significant energy exists at high frequencies, the effect can be eliminated using an external track-and-hold amplifier to allow the ar- rays charge current to decay, thereby eliminating any voltage drop across the switches. since the cs5014/16 has a second sampling function on- chip, the external track-and-hold can return to the track mode once the converters hold input falls. it need only acquire the analog input by the time the entire conversion cycle finishes. code (hexadecimal) counts: 0 11 911 3470 599 9 0 80cb 80cc 80cd 80cf 80d0 80ce 80ca 1000 2000 3000 4000 5000 count noiseless cs5016 converter figure 30. histogram plot of 5000 conversion inputs from the cs5016 cs5012a, cs5014, cs5016 ds14f6 2-35
clock feedthrough in the cs5014 and cs5016 maintaining the integrity of analog signals in the presence of digital switching noise is a difficult problem. the cs5014/16 can be synchronized to the digital system using the clkin input to avoid conversion errors due to asynchronous in- terference. however, digital interference will still affect sampling purity due to coupling between the cs5014/16s analog input and master clock. the effect of clock feedthrough depends on the sampling conditions. if the sampling signal at the hold input is synchronized to the master clock, clock feedthrough will appear as a dc offset at the cs5014/16s output. the offset could theoreti- cally reach the peak coupling magnitude (figure 35), but the probability of this occurring is small since the peaks are spikes of short dura- tion. if sampling is performed asynchronously with the master clock, clock feedthrough will appear as an ac error at the cs5014/16s output. with a fixed analog input source impedance 200 25 50 50 50 4mhz 2mhz master clock clock feedthrough int/ext freq internal external external external external 2mhz 4mhz 4mhz rms peak-to-peak 15uv 25uv 40uv 25uv 80uv 70uv 110uv 150uv 110uv 325uv figure 35. examples of measured clock feedthrough signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 81.5 db 12 khz figure 31. cs5014 fft plot with 12 khz full scale input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 84.3 db 12 khz figure 33. cs5016 fft plot with 12 khz full scale input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 25 khz sampling rate: 50 khz full scale: 9v p-p s/(n+d): 71.9 db 12 khz figure 34. cs5016 fft plot with 12 khz -20 db input signal amplitude relative to full scale dc input frequency 0db -20db -40db -60db -80db -100db -120db 28 khz sampling rate: 56 khz full scale: 9v p-p s/(n+d): 64.6 db 12 khz figure 32. cs5014 fft plot with 12 khz -20 db input cs5012a, cs5014, cs5016 2-36 ds14f6
sampling rate, a tone will appear as the clock fre- quency aliases into the baseband. the tone frequency can be calculated using the equation below and could be selectively filtered in soft- ware using dsp techniques. f tone = (n f s - f clk ) where n = f clk /f s rounded to the nearest integer the magnitude of clock feedthrough depends on the master clock conditions and the source im- pedance applied to the analog input. when operating with the cs5014/16s internally gener- ated clock, the clkin input is grounded and the dominant source of coupling is through the de- vices substrate. as shown in figure 35, a typical cs5014/16 operating with their internal oscillator at 2 mhz and 50 w of analog input source im- pedance will exhibit only 15 m v rms of clock feedthrough. however, if a 2 mhz external clock is applied to clkin under the same conditions, feedthrough increases to 25 m v rms. feedthrough also increases with clock frequency; a 4 mhz clock yields 40 m v rms. clock feedthrough can be reduced by limiting the source impedance applied at the analog input. as shown in figure 35, reducing source impedance from 50 w to 25 w yields a 15 m v rms reduction in feedthrough. therefore, when operating the cs5014/16 with high-frequency external master clocks, it is important to minimize source imped- ance applied to the cs5014/16s input. also, the overall effect of clock feedthrough can be minimized by maximizing the input range and lsb size. the reference voltage applied to vref can be maximized, and the cs5014/16 can be op- erated in bipolar mode which inherently doubles the lsb size over the unipolar mode. differences between the cs5012a and the cs5012 the differences between the cs5012a and the cs5012 are tabulated in table 3. the cs5012 is a short-cycled version of the cs5016 a/d con- verter and includes the same 18-bit calibration circuitry. this calibration circuitry sets the cali- bration resolution of the cs5012 at 1/64th of an lsb and achieves the near perfect differential linearity performance illustrated by the cs5012 dnl plot in figure 15. the cs5012a calibration circuitry was modified to provide calibration to 15-bit resolution therefore achieving calibration to 1/8 of an lsb. this reduction in calibration resolution for the cs5012a reduces the time re- quired to calibrate the device (see table 3) and reduces the size of the total array capacitance. the reduced array capacitance improves the high frequency performance by allowing higher slew rate in the input circuitry. table 3 documents some other improvements in- cluded in the cs5012a. the burst mode calibration was made functional, although it should not be used. the device was also modified so the eoc signal goes low at the end of a reset calibration in either microprocessor or microproc- essor-independent mode. the cs5012a was modified to maintain a throughput rate of 64 clkin cycles in loopback mode for all frequen- cies of clkin. schematic & layout review service confirm optimum schematic & layout before building your board. for our free review service call applications engineering. call: (512) 445-7222 cs5012a, cs5014, cs5016 ds14f6 2-37
calibration resolution calibration time reset: interleave: burst: end of calibration indicator throughput rate in loopback mode input capacitance in fine-charge mode cs5012 18 bits. results in dnl calibration to 1/64 lsb at 12 bits. 1,441,020 clkin cycles 72,051 conversions not functional eoc falls at the completion of a reset calibration cycle in microprocessor mode only. in microprocessor-independent mode cycles after completion of a reset calibration. the device acquires and converts in 64 clkin cycles for clkin=4mhz, but will require 68 clkin cycles at 100khz through- put. this is due to excess delay on 275pf typical, unipolar mode cs5012a 15 bits. results in dnl calibration to 1/8 lsb at 12 bits. 58,280 clkin cycles 2,014 conversions fully functional eoc falls in either microprocessor or microprocessor-independent mode at the completion of a reset calibration cycle. the device acquires and converts a sample in 64 clkin cycles for all clkin frequencies when in loopback. 103pf typical, unipolar mode eot must be used. eot. slew rate unipolar coarse charge fine charge bipolar coarse charge fine charge falls 15 clkin eot 20v/us 1.5v/us 40v/us 3.0v/us 5v/us 0.25v/us 10v/us 0.5v/us 72pf typical, bipolar mode 165pf typical, bipolar mode table 3. differences between the cs5012a and cs5012 cs5012a, cs5014, cs5016 2-38 ds14f6
figure 36. cs5012a/14/16 system connection diagram 26 28 29 30 25 27 11 10 36 vref ain refbuf va- agnd va+ vd+ dgnd vd- +5v -5v 10 w 10 w voltage reference reset generator data processor serial data interface (optional) clock source (optional) control logic mode select * analog supply source signal analog supply analog tst bw reset a0 cal d0-d15 sclk sdata clkin 24 33 20 40 39 8 or 16 38 37 1 35 34 21 22 23 32 31 0.1 m f 0.01 m f 0.1 m f 0.1 m f may be microprocessor or discrete logic. 0.1 m f intrlv eoc eot hold bp/up rd cs 0.1 m f cs5012a or vref vref 0 10 m f signal conditioning 1000 pf 200 w cs5014 cs5016 unused logic inputs should only be connected to vd+ or dgnd. * bw and bp/up should always be terminated to vd+ or dgnd, for best dynamic s/(n+d) performance. or driven by a logic gate. function rst a0 cal hold and start convert initiate burst calibration stop burst cal and begin track initiate interleave calibration terminate interleave cal read output data read status register high impedance data bus high impedance data bus reset reset 0 0 0 0 0 0 0 x x 1 x * * * * * 1 0 * * x 0 x x x x x 0 0 x 1 x x x x x 0 1 x x x x x x x 1 0 x x x x x x x x x 0 0 0 0 0 0 1 x x 0 x 1 x x x 1 x x x 0 hold cs intrlv rd table 4. cs5012a/14/16 truth table * the status of a0 is not critical to the operation specified. however, a0 should not be low with cs and hold low, or a software reset will result. cs5012a, cs5014, cs5016 ds14f6 2-39
hold hold sdata serial output cs5016 (lsb) data bus bit 0 d0 sclk serial clock data bus bit 1 d1 eoc end of conversion cs5014 (lsb) data bus bit 2 d2 eot end of track data bus bit 3 d3 vd- negative digital power cs5012 (lsb) data bus bit 4 d4 cal calibrate data bus bit 5 d5 intrlv interleave data bus bit 6 d6 bw bus width select data bus bit 7 d7 rst reset digital ground dgnd tst test positive digital power vd+ va- negative analog power data bus bit 8 d8 refbuf reference buffer output data bus bit 9 d9 vref voltage reference data bus bit 10 d10 agnd analog ground data bus bit 11 d11 ain analog input data bus bit 12 d12 va+ positive analog power data bus bit 13 d13 bp / up bipolar/unipolar select data bus bit 14 d14 a0 read address (msb) data bus bit 15 d15 rd read clock input clkin cs chip select hold d0 sdata d1 sclk d2 eoc d3 eot d4 vd- d5 cal d6 intrlv nc bw d7 rst dgnd tst vd+ va- nc nc d8 refbuf nc vref d9 agnd d10 ain d11 va+ d12 bp/ up d13 a0 d14 rd d15 cs clkin cs5012a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 cs5012 cs5014 cs5016 top view 18 20 22 24 26 28 1 2 4 640 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 cs5012a cs5012 cs5014 cs5016 note: all pin references in this data sheet refer to the 40-pin dip package numbering. use this figure to determine pin numbers for 44-pin package. cs5012a, cs5014, cs5016 2-40 ds14f6
pin descriptions power supply connections vd+ C positive digital power, pin 11. positive digital power supply. nominally +5 volts. vd- C negative digital power, pin 36. negative digital power supply. nominally -5 volts. dgnd C digital ground, pin 10. digital ground. va+ C positive analog power, pin 25. positive analog power supply. nominally +5 volts. va- C negative analog power, pin 30. negative analog power supply. nominally -5 volts. agnd C analog ground, pin 27. analog ground. oscillator clkin C clock input, pin 20. all conversions and calibrations are timed from a master clock which can either be supplied by driving this pin with an external clock signal, or can be internally generated by tying this pin to dgnd. digital inputs hold C hold, pin 1. a falling transition on this pin sets the cs5012a/14/16 to the hold state and initiates a conversion. this input must remain low at least one clkin cycle plus 50 ns. cs C chip select, pin 21. when high, the data bus outputs are held in a high impedance state and the input to cal and intrlv are ignored. a falling transition initiates or terminates burst or interleave calibration (depending on the status of cal and intrlv) and a rising transition latches both the cal and intrlv inputs. if rd is low, the data bus is driven as indicated by bw and a0. rd C read, pin 22. when rd and cs are both low, data is driven onto the data bus. if either signal is high, the data bus outputs are held in a high impedance state. the data driven onto the bus is determined by bw and a0. cs5012a, cs5014, cs5016 ds14f6 2-41
a0 C read address, pin 23. determines whether data or status information is placed onto the data bus. when high during the read operation, converted data is placed onto the data bus; when low, the status register is driven onto the bus. bp/ up C bipolar/unipolar input select, pin 24. when high, the device is configured with a bipolar transfer function ranging from -vref to +vref. encoding is in an offset binary format, with the mid-scale code 100...0000 centered at agnd. when low, the device is configured for a unipolar transfer function from agnd to vref. unipolar encoding is in straight binary format. once calibration has been performed, either bipolar or unipolar mode may be selected without the need to recalibrate. rst C reset, pin 32. when taken high for at least 100 ns, all internal digital logic is reset. upon being taken low, a full calibration sequence is initiated. bw C bus width select, pin 33. when hard-wired high, all 12 data bits are driven onto the bus simultaneously during a data read cycle. when low, the bus is in a byte wide format. on the first read following a conversion, the eight msbs are driven onto d0-d7. a second read cycle places the four lsbs with four trailing zeros on d0-d7. subsequent reads will toggle the higher/lower order byte. regardless of bws status, a read cycle with a0 low yields the status information on d0-d7. intrlv C interleave, pin 34. when latched low using cs, the device goes into interleave calibration mode. a full calibration will complete every 2,014 conversions in the cs5012a, and every 72,051 conversions in the cs5014/16. the effective conversion time extends by 20 clock cycles. cal C calibrate, pin 35. (see addendum appending this data sheet)) when latched high using cs, burst calibration results. the device cannot perform conversions during the calibration period which will terminate only once cal is latched low again. calibration picks up where the previous calibration left off, and calibration cycles complete every 58,280 clkin cycles in the cs5012a, and every 1,441,020 clkin cycles in the cs5014/16 . if the device is converting when a calibration is signaled, it will wait until that conversion completes before beginning. analog inputs ain C analog input, pin 26. input range in the unipolar mode is zero volts to vref. input range in bipolar mode is -vref to +vref. the output impedance of buffer driving this input should be less than or equal to 200 w . cs5012a, cs5014, cs5016 2-42 ds14f6
vref C voltage reference, pin 28. the analog reference voltage which sets the analog input range. it represents positive full scale for both bipolar and unipolar operation, and its magnitude sets negative full scale in bipolar mode. digital outputs d0 through d15 C data bus outputs, pins 2 thru 9, 12 thru 19. 3-state output pins. enabled by cs and rd, they offer the converters output in a format consistent with the state of bw if a0 is high. if a0 is low, bits d0-d7 offer status register data. eot C end of track, pin 37. if low, indicates that enough time has elapsed since the last conversion for the device to acquire the analog input signal. eoc C end of conversion, pin 38. this output indicates the end of a conversion or calibration cycle. it is high during a conversion and will fall to a low state upon completion of the conversion cycle indicating valid data is available at the output. returns high on the first subsequent read or the start of a new conversion cycle. sdata C serial output, pin 40. presents each output data bit after it is determined by the successive approximation algorithm. valid on the rising edge of sclk, data appears msb first, lsb last, and each bit remains valid until the next bit appears. sclk C serial clock output, pin 39. used to clock converted output data serially from the cs5012a/14/16. serial data is stable on the rising edge of sclk. analog outputs refbuf C reference buffer output, pin 29. reference buffer output. a 0.1 m f ceramic capacitor must be tied between this pin and va-. miscellaneous tst C test, pin 31. allows access to the cs5012a/14/16s test functions which are reserved for factory use. must be tied to dgnd. cs5012a, cs5014, cs5016 ds14f6 2-43
parameter definitions linearity error the deviation of a code from a straight line passing through the endpoints of the transfer function after zero- and full-scale errors have been accounted for. "zero-scale" is a point 1/2 lsb below the first code transition and "full-scale" is a point 1/2 lsb beyond the code transition to all ones. the deviation is measured from the middle of each particular code. units in % full-scale. differential linearity minimum resolution for which no missing codes is guaranteed. units in bits. full scale error the deviation of the last code transition from the ideal (vref-3/2 lsbs). units in lsbs. unipolar offset the deviation of the first code transition from the ideal (1/2 lsb above agnd) when in unipolar mode (bp/up low). units in lsbs. bipolar offset the deviation of the mid-scale transition (011...111 to 100...000) from the ideal (1/2 lsb below agnd) when in bipolar mode (bp/ up high). units in lsbs. bipolar negative full-scale error the deviation of the first code transition from the ideal when in bipolar mode (bp/ up high). the ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. units in lsbs. peak harmonic or spurious noise (more accurately, signal to peak harmonic or spurious noise) the ratio of the rms value of the signal to the rms value of the next largest spectral component below the nyquist rate (excepting dc). this component is often an aliased harmonic when the signal frequency is a significant proportion of the sampling rate. expressed in decibels. total harmonic distortion the ratio of the rms sum of all harmonics to the rms value of the signal. units in percent. signal-to-noise ratio the ratio of the rms value of the signal to the rms sum of all other spectral components below the nyquist rate (excepting dc), including distortion components. expressed in decibels. aperture time the time required after the hold command for the sampling switch to open fully. effectively a sampling delay which can be nulled by advancing the sampling signal. units in nanoseconds. aperture jitter the range of variation in the aperture time. effectively the "sampling window" which ultimately dictates the maximum input signal slew rate acceptable for a given accuracy. units in picoseconds. note: temperatures specified define ambient conditions in free-air during test and do not refer to the junction temperature of the device. cs5012a, cs5014, cs5016 2-44 ds14f6
cs5012a ordering guide model throughput conversion time maximum dnl temp. range package CS5012A-KP12 63 khz 12.25 m s 1/2 lsb 0 to 70 c 40-pin plastic dip cs5012a-kp7 100 khz 7.20 m s 1/2 lsb 0 to 70 c 40-pin plastic dip cs5012a-kl12 63 khz 12.25 m s 1/2 lsb 0 to 70 c 44-pin plcc cs5012a-kl7 100 khz 7.20 m s 1/2 lsb 0 to 70 c 44-pin plcc cs5012a-bp12 63 khz 12.25 m s 1/2 lsb -40 to +85 c 40-pin plastic dip cs5012a-bp7 100 khz 7.20 m s 1/2 lsb -40 to +85 c 40-pin plastic dip cs5012a-bl12 63 khz 12.25 m s 1/2 lsb -40 to +85 c 44-pin plcc cs5012a-bl7 100 khz 7.20 m s 1/2 lsb -40 to +85 c 44-pin plcc 5962-8967901qa 63 khz 12.25 m s 1/2 lsb -55 to +125 c 40-pin cerdip 5962-8967901xa 63 khz 12.25 m s 1/2 lsb -55 to +125 c 44-pin ceramic lcc the cs5012a is recommended for new designs. the following is a list of upgraded part numbers. discontinued equivalent part number recommended device. cs5012-kp24 CS5012A-KP12 cs5012-kp12 CS5012A-KP12 cs5012-kp7 cs5012a-kp7 cs5012-kl24 cs5012a-kl12 cs5012-kl12 cs5012a-kl12 cs5012-kl7 cs5012a-kl7 cs5012-bd24 cs5012a-bp12 cs5012-bd12 cs5012a-bp12 cs5012-bd7 cs5012a-bp7 cs5012-bl24 cs5012a-bl12 cs5012-bl12 cs5012a-bl12 cs5012-bl7 cs5012a-bl7 cs5012-td24b 5962-897901qa cs5012-td12b 5962-897901qa cs5012-te24b 5962-897901xa cs5012-te12b 5962-897901xa cs5012a, cs5014, cs5016 ds14f6 2-45
cs5014 ordering guide model throughput conversion time linearity temp. range package cs5014-kp28 28 khz 28.50 m s 0.5 lsb 0 to 70 c 40-pin plastic dip cs5014-kp14 56 khz 14.25 m s 0.5 lsb 0 to 70 c 40-pin plastic dip cs5014-kl28 28 khz 28.50 m s 0.5 lsb 0 to 70 c 44-pin plcc cs5014-kl14 56 khz 14.25 m s 0.5 lsb 0 to 70 c 44-pin plcc cs5014-bp28 28 khz 28.50 m s 0.5 lsb -40 to +85 c 40-pin plastic dip cs5014-bp14 56 khz 14.25 m s 0.5 lsb -40 to +85 c 40-pin plastic dip cs5014-bl28 28 khz 28.50 m s 0.5 lsb -40 to +85 c 44-pin plcc cs5014-bl14 56 khz 14.25 m s 0.5 lsb -40 to +85 c 44-pin plcc cs5014-sd14 56 khz 14.25 m s 1.5 lsb -55 to +125 c 40-pin cerdip cs5014-td14 56 khz 14.25 m s 0.5 lsb -55 to +125 c 40-pin cerdip cs5014-se14 56 khz 14.25 m s 1.5 lsb -55 to +125 c 44-pin ceramic lcc cs5014-te14 56 khz 14.25 m s 0.5 lsb -55 to +125 c 44-pin ceramic lcc 5962-8967401qa 56 khz 14.25 m s 1.5 lsb -55 to +125 c 40-pin cerdip 5962-8967402qa 56 khz 14.25 m s 0.5 lsb -55 to +125 c 40-pin cerdip 5962-8967401xa 56 khz 14.25 m s 1.5 lsb -55 to +125 c 44-pin ceramic lcc 5962-8967402xa 56 khz 14.25 m s 0.5 lsb -55 to +125 c 44-pin ceramic lcc the following is a list of upgraded part numbers. discontinued equivalent part number recommended device cs5014-sd14b 5962-8967401qa cs5014-td14b 5962-8967402qa cs5014-se14b 5962-8967401xa cs5014-te14b 5962-8967402xa cs5012a, cs5014, cs5016 2-46 ds14f6
cs5016 ordering guide signal to model linearity noise ratio conversion time temp. range package cs5016-jp32 .0030% 87 db 32.50 m s 0 to 70 c 40-pin plastic dip cs5016-jp16 .0030% 87 db 16.25 m s 0 to 70 c 40-pin plastic dip cs5016-kp32 .0015% 90 db 32.50 m s 0 to 70 c 40-pin plastic dip cs5016-kp16 .0015% 90 db 16.25 m s 0 to 70 c 40-pin plastic dip cs5016-jl32 .0030% 87 db 32.50 m s 0 to 70 c 44-pin plcc cs5016-jl16 .0030% 87 db 16.25 m s 0 to 70 c 44-pin plcc cs5016-kl32 .0015% 90 db 32.50 m s 0 to 70 c 44-pin plcc cs5016-kl16 .0015% 90 db 16.25 m s 0 to 70 c 44-pin plcc cs5016-ap32 .0030% 87 db 32.50 m s -40 to +85 c 40-pin plastic dip cs5016-ap16 .0030% 87 db 16.25 m s -40 to +85 c 40-pin plastic dip cs5016-bp32 .0015% 90 db 32.50 m s -40 to +85 c 40-pin plastic dip cs5016-bp16 .0015% 90 db 16.25 m s -40 to +85 c 40-pin plastic dip cs5016-al32 .0030% 87 db 32.50 m s -40 to +85 c 44-pin plcc cs5016-al16 .0030% 87 db 16.25 m s -40 to +85 c 44-pin plcc cs5016-bl32 .0015% 90 db 32.50 m s -40 to +85 c 44-pin plcc cs5016-bl16 .0015% 90 db 16.25 m s -40 to +85 c 44-pin plcc cs5016-sd16 .0076% 87 db 16.25 m s -55 to +125 c 40-pin cerdip cs5016-td16 .0015% 90 db 16.25 m s -55 to +125 c 40-pin cerdip cs5016-se16 .0076% 87 db 16.25 m s -55 to +125 c 44-pin ceramic lcc cs5016-te16 .0015% 90 db 16.25 m s -55 to +125 c 44-pin ceramic lcc 5962-8967601qa .0076% 87 db 16.25 m s -55 to +125 c 40-pin cerdip 5962-8967602qa .0015% 90 db 16.25 m s -55 to +125 c 40-pin cerdip 5962-8967601xa .0076% 87 db 16.25 m s -55 to +125 c 44-pin ceramic lcc 5962-8967602xa .0015% 90 db 16.25 m s -55 to +125 c 44-pin ceramic lcc the following is a list of upgraded part numbers. discontinued equivalent part number recommended device cs5016-sd16b 5962-8967601qa cs5016-td16b 5962-8967602qa cs5016-se16b 5962-8967601xa cs5016-te16b 5962-8967602xa cs5012a, cs5014, cs5016 ds14f6 2-47
millimeters inches dim min max min max d b a l c 13.72 51.69 1.02 0.36 0.51 3.94 3.18 0.20 0 2.41 15.24 14.22 52.71 1.65 0.56 1.02 5.08 3.81 0.38 15 0.540 2.035 0.095 0.040 0.014 0.020 0.155 0.125 0.600 0.008 0 0.560 2.075 0.065 0.022 0.040 0.200 0.150 0.015 15 40 pin plastic dip 1 40 21 20 15.87 0.625 e1 d b seating plane a b1 e1 a1 l c ea 2.67 0.105 notes: 1. positional tolerance of leads shall be within 0.25mm (0.010") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 3. dimension e1 does not include mold flash. nom 13.97 52.20 1.27 0.46 0.76 4.32 - 0.25 - 2.54 - nom 0.550 2.055 0.100 0.050 0.018 0.030 0.170 - - 0.010 - a1 b1 e1 e1 ea
e e1 d1 d d2/e2 44 pin plcc no. of terminals d2/e2 max min max min millimeters inches dim a d/e 17.65 17.40 0.685 b e a a1 b e 0.695 16.66 16.51 0.650 0.656 4.57 4.20 0.180 0.165 0.53 0.33 0.021 0.013 2.29 0.090 16.00 14.99 0.590 0.630 1.19 1.35 0.047 0.053 nom 17.53 16.59 4.45 0.41 2.79 15.50 1.27 nom 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 d1/e1 a1
notes: 1. positional tolerance of leads shall be within 0.13mm (0.005") at maximum material condition, in relation to seating plane and each other. 2. dimension ea to center of leads when formed parallel. 40 pin cerdip 1 40 21 20 e1 d b seating plane a b1 e1 a1 l c ea 0.46 0.25 52.32 14.73 2.54 15.24 3.81 0.018 0.010 2.060 0.580 0.100 0.600 0.150 12.70 50.29 1.27 0.38 0.51 4.06 2.92 0.20 5 2.41 15.11 15.37 52.57 1.65 0.56 1.27 5.84 4.06 0.30 15 15.37 2.67 0.500 1.980 0.095 0.050 0.015 0.020 0.160 0.115 0.595 0.008 5 0.605 2.070 0.065 0.022 0.050 0.230 0.160 0.012 15 0.605 0.105 millimeters inches dim min max min e1 d e1 b1 b a1 a l ea c nom nom max
28 44 no. of terminals max min max min max min max min millimeters millimeters inches inches dim a 3.43 2.54 0.135 0.100 3.43 2.54 0.135 0.100 b 0.58 0.33 0.023 0.013 0.58 0.33 0.023 0.013 0.81 0.51 0.032 0.02 b1 0.81 0.51 0.032 0.02 d2 1 e1 top view d1 e d 28/44 pin clcc a b b1 e1 d4/e4 nom 3.05 0.46 nom 0.120 0.018 nom 3.05 0.46 nom 0.120 0.018 e2 d/e 0.660 0.640 16.26 16.76 17.78 0.700 17.27 0.680 12.19 12.70 11.18 11.68 0.480 0.500 0.440 0.460 e1 1.40 1.14 0.055 0.045 1.40 1.14 0.055 0.045 d2/e2 0.505 0.495 12.57 12.83 7.49 7.75 0.295 0.305 d4/e4 0.635 0.625 15.88 16.13 10.80 11.05 0.425 0.435 12.46 11.43 1.27 7.62 10.92 0.490 0.450 0.050 0.300 0.430 16.51 17.53 1.27 12.70 16.00 0.650 0.690 0.050 0.500 0.630 0.64 0.025 0.64 0.025 d1/e1
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